View CY62157ESL-45ZSXI_4156999.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62157ESL MoBL(R)
8-Mbit (512K x 16) Static RAM
Features

Very high speed: 45 ns Wide voltage range: 2.2V-3.6V and 4.5V-5.5V Ultra low standby power Typical Standby current: 2 A Maximum Standby current: 8 A Ultra low active power Typical active current: 1.8 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 44-pin TSOP II package
into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input or output pins (IO0 through IO15) are placed in a high impedance state when:

Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 10 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Functional Description
The CY62157ESL is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
512K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
Power Down Circuit
CE BHE WE CE OE BLE
A12 A13
A15
A11
BLE
Cypress Semiconductor Corporation Document #: 001-43141 Rev. **
*
198 Champion Court
A14
A17 A18
A16
BHE
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 04, 2008
[+] Feedback
CY62157ESL MoBL(R)
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View)
A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A18 A17 A16 A15 A14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 A8 A9 A10 A11 A12 A13
Product Portfolio
Power Dissipation Product Range VCC Range (V) [1] Speed (ns) Operating ICC, (mA) f = 1MHz Typ CY62157ESL Industrial 2.2V-3.6V and 4.5V-5.5V 45
[2]
f = fmax Typ [2] 18 Max 25
Standby, ISB2 (A) Typ [2] 2 Max 8
Max 3
1.8
Notes 1. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3V, and VCC = 5V, TA = 25C.
Document #: 001-43141 Rev. **
Page 2 of 12
[+] Feedback
CY62157ESL MoBL(R)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential..................-0.5V to 6.0V DC Voltage Applied to Outputs in High-Z State[3, 4] ...........................................-0.5V to 6.0V DC Input Voltage[3, 4] ........................................-0.5V to 6.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA
Operating Range
Device CY62157ESL Range Industrial Ambient Temperature -40C to +85C VCC[5] 2.2V-3.6V, and 4.5V-5.5V
Electrical Characteristics
Over the Operating Range 45 ns Parameter VOH Description Output HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VOL Output LOW Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIH Input HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIL Input LOW Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 IIX IOZ ICC Input Leakage Current VCC Operating Supply Current GND < VI < VCC f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA, CMOS levels Output Leakage Current GND < VO < VCC, Output Disabled Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1mA IOL = 2.1mA 1.8 2.2 2.2 -0.3 -0.3 -0.5 -1 -1 18 1.8 2 Min 2.0 2.4 2.4 0.4 0.4 0.4 VCC + 0.3 VCC + 0.3 VCC + 0.5 0.6 0.8 0.8 +1 +1 25 3 8 A A A mA V V V Typ [2] Max Unit V
ISB1
ISB2
Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, down Current -- CMOS f = fmax (Address and Data Only), Inputs f = 0 (OE, BHE, BLE and WE), VCC = VCC(max) Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, down Current -- CMOS f = 0, VCC = VCC(max) Inputs
2
8
A
Notes 3. VIL(min) = -2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
Document #: 001-43141 Rev. **
Page 3 of 12
[+] Feedback
CY62157ESL MoBL(R)
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP II 77 13 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE VCC 10% GND R2 Rise Time = 1 V/ns Equivalent to: ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
THEVENIN EQUIVALENT RTH OUTPUT V TH 5.0V 1800 990 639 1.77 Unit V
Parameters R1 R2 RTH VTH
2.5V 16667 15385 8000 1.20
3.0V 1103 1554 645 1.75
Document #: 001-43141 Rev. **
Page 4 of 12
[+] Feedback
CY62157ESL MoBL(R)
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR
[6]
Description VCC for Data Retention Data Retention Current
Conditions
Min 1.5
Typ[2]
Max
Unit V
CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V
VCC = 1.5V VCC = 2.0V 0 tRC
2 2
5 8
A
tCDR tR [7]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE or BHE.BLE
[8]
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 8. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 001-43141 Rev. **
Page 5 of 12
[+] Feedback
CY62157ESL MoBL(R)
Switching Characteristics
Over the Operating Range [9] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z[10, 11]
[10]
Description
45 ns Min 45 45 10 45 22 5 18 10 18 0 45 45 5 18 45 35 35 0 0 35 35 25 0 18 10 Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW-Z[10] OE HIGH to High-Z[10, 11] CE LOW to Low-Z[10] CE HIGH to High-Z[10, 11] CE LOW to Power Up CE HIGH to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to BLE/BHE HIGH to Low-Z[10, 12] HIGH-Z[10, 11]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
WE HIGH to Low-Z
Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. If both byte enables are toggled together, this value is 10 ns. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-43141 Rev. **
Page 6 of 12
[+] Feedback
CY62157ESL MoBL(R)
Switching Waveforms
Figure 2. Read Cycle No.1: Address Transition Controlled. [14, 15]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 3. Read Cycle No. 2: OE Controlled [15, 16]
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE HIGHIMPEDANCE DATA OUT tLZCE tPU VCC SUPPLY CURRENT 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 14. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 15. WE is HIGH for read cycle. 16. Address valid before or similar to CE, BHE, BLE transition LOW.
Document #: 001-43141 Rev. **
Page 7 of 12
[+] Feedback
CY62157ESL MoBL(R)
Switching Waveforms (continued)
Figure 4. Write Cycle No 1: WE Controlled [13, 17, 18]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE NOTE 19 tHZOE
tSD DATAIN
tHD
DATA IO
Figure 5. Write Cycle 2: CE Controlled [13, 17, 18]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 19 tHZOE
Notes 17. Data IO is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period, the IOs are in output state. Do not apply input signals.
tHD
DATAIN
Document #: 001-43141 Rev. **
Page 8 of 12
[+] Feedback
CY62157ESL MoBL(R)
Switching Waveforms (continued)
Figure 6. Write Cycle 3: WE controlled, OE LOW [18]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATA IO NOTE 19 tHZWE DATAIN
tHD
tLZWE
Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [18]
tWC ADDRESS
CE tSCE
tAW tHA tBW tSA
BHE/BLE
WE
tHZWE
tPWE tSD DATAIN
tLZWE
tHD
DATA IO
NOTE 19
Document #: 001-43141 Rev. **
Page 9 of 12
[+] Feedback
CY62157ESL MoBL(R)
Truth Table
CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High-Z High-Z Data Out (IO0-IO15) Data Out (IO0-IO7); IO8-IO15 in High-Z Data Out (IO8-IO15); IO0-IO7 in High-Z High-Z High-Z High-Z Data In (IO0-IO15) Data In (IO0-IO7); IO8-IO15 in High-Z Data In (IO8-IO15); IO0-IO7 in High-Z Mode Deselect/Power down Deselect/Power down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62157ESL-45ZSXI Package Diagram Package Type Operating Range Industrial
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Document #: 001-43141 Rev. **
Page 10 of 12
[+] Feedback
CY62157ESL MoBL(R)
Package Diagrams
Figure 8. 44-Pin TSOP II, 51-85087
51-85087-*A
Document #: 001-43141 Rev. **
Page 11 of 12
[+] Feedback
CY62157ESL MoBL(R)
Document History Page
Document Title: CY62157ESL MoBL(R) 8-Mbit (512K x 16) Static RAM Document Number: 001-43141 REV. ** ECN NO. 1875228 Issue Date See ECN Orig. of Change Description of Change
VKN/AESA New Data Sheet
(c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43141 Rev. **
Revised January 04, 2008
Page 12 of 12
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY62157ESL-45ZSXI

	To Download CY62157ESL-45ZSXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .